1. Field of the Invention
The present invention relates generally to Field Programmable Gate Arrays (FPGAs). More particularly, the present invention relates to an apparatus and method for compressing data streams used to program FPGAs and for decreasing the amount of time necessary to configure FPGAs.
2. Related Art
In Field Programmable Gate Arrays (FPGAs), Resource Routing Nodes (R-Nodes) are used to connect logic elements of the FPGAs, which may also be configurable, through Configurable Interconnect Points (CIPs). To implement a desired circuit, the FPGA must be given the information as to what connections are to be made and/or what logic is to be implemented. This is generally accomplished by employing a "configuration bitstream," which is an ordered data stream in which each bit is represented by a binary value (e.g., logic 1 or logic 0).
The configuration bitstream is generally used to configure (i.e., program) switches inside the FPGA to a desired state, (e.g., on or off). These switches can be implemented from RAM cells which control pass transistors, antifuse connection points, fuse connection points, or any other type of switch implementation. These switches are then used to control the configurable routing or logic on the FPGA.
The switches in an FPGA are typically arranged in a M row by N column matrix (array). Therefore, the bitstream is generally broken up into "frames," where each frame contains control bits along with data needed to write to one column of the array.
FIG. 1 shows a simplified block diagram illustrating how current FPGAs are generally programmed. Data bits (configuration bitstream 101) are shifted through a data shift register 102 one bit at a time per clock cycle. Data bits are shifted until the data bits align with the appropriate row, at which time the appropriate column of switches is written to by enabling the column's address line 108, 110, or 112. Thus, one frame of data is used to program one column of switches, followed by the next frame of data used to program the next consecutive column of switches (usually loaded from left to right starting with column 0 in FIG. 1 ). This is continued until all columns of switches have been set appropriately. Thus, for the entire FPGA, there is a corresponding set of data bits in the configuration bitstream 101 for each switch to be set.
As the size (usable gate count) of FPGAs increasingly become larger, the number of switches in an FPGA will increase appreciably. As a consequence the configuration bitstream becomes larger, making the configuration bitstream difficult to manage and store. For example, an FPGA with 15,000 usuable gates requires a bit stream of 192,000 bits. Therefore, what is needed is a methodology to reduce the size of the bit stream.
Another problem associated with configuring FPGAs is the amount of time it takes to configure (program) the FPGA. In current FPGA designs one frame of data bits is shifted through the data shift register one bit per clock cycle. Thus, the amount of time it takes to configure the FPGA can be considerable, especially during device testing where it is common to reconfigure the FPGA many times. Therefore, what is needed is a methodology to speed-up the time it takes to configure FPGAs.